1. Field of the Invention
The present invention generally relates to clock distribution systems, and more particularly to a clock distribution system which utilizes multiple clock sourcing circuitry to simultaneously clock a plurality of circuit loads.
2. Description of the Prior Art
Modern digital circuitry requires the use of a synchronous clock to provide timing for the computational and control functions. It is this synchronization which renders the digital sequential machine capable of theoretically absolute repeatability. These synchronous systems are digital systems wherein the operations are controlled by continuous, periodic clock pulses. This allows activity within the system to occur at a fixed time relative to the pulses of the synchronous clock.
Synchronous computer systems also use a number of different memory elements. These memory elements are typically synchronous and therefore require the clock signal. In addition, these memory elements can be "edge triggered" which means that new data is stored in the memory element on a particular edge of the clock (for example on the low to high transition). If a digital circuit that contains synchronous memory elements loses the clock signal, the circuit will cease to function. In addition, if there is a "glitch" on the clock line (a glitch being defined as an undesired spike of voltage) the synchronous memory elements may load erroneous data because typically they are edge triggered and the glitch will be interpreted as an "edge". Therefore, it is vital to any digital system to have a reliable and glitch free clock signal.
In electronic circuitry requiring digital synchronous clock signals, reliability concerns often dictate the use identical redundant clock signals within a given system. The purpose of the redundant clock signals is to provide a substitute clock signal should the primary clock signal fail. The problem presented with multiple redundant clock sources is the need to switch between them to preserve system operation following failure of the main clock source. Typically, a voting method is used to generate the primary clock signal. An example of such a circuit is discussed in U.S. Pat. No. 4,644,498, issued to Bedard et al. This type of circuit simply has an odd number of identical clock sourcing circuits so that the failure of a minority of the clock sourcing circuits will not cause the entire system to fail. Therefore, this type of circuit does not really switch between clock signals but rather it generates a new signal based on the voting scheme.
The major problem with the voting approach is that the complex circuitry required to implement the voting process may provide an actual decrease in reliability when measured at the system level. This occurs because, though this approach provides protection against failure of a clock source, it adds the voting circuitry as a critical element. Therefore, a failure of the voting circuit can disable the system even though failures of an individual clock source do not. Oftentimes, the reliability of the voting circuit is less than that of an individual clock source, thus decreasing overall system reliability.
In addition to reliability concerns, it may also be necessary to switch between different clock sources during mode changes in normal operation. It is known, for example, to have different frequency clock signals within a given system. Typically, a given element within a system will only use one of a plurality of different frequency clock signals. Therefore, no clock switching is required for that element. However, some applications require that a given element within a system run with various frequency clock signals at different times or in different modes. An example of this would be a microprocessor which has a functional mode and a self test mode. Typically the microprocessor will run using a functional clock in functional mode and using a test clock in test mode. The frequency of the functional clock will typically be much higher than that of the test clock. Though undesirable, the switch between such a functional clock and a test clock can be accomplished by disabling the operation of the system during the switching process.